Wednesday, November 15, 2017
Module 4 (2nd half) and Module 5 (1st half)
Module 4 (2nd half) and Module 5 (1st half) COUNTERS notes
Saturday, November 11, 2017
Module 1 (1st half) NOTES
Module 1 (1st half) NOTES
- JFET
- MOSFET
- Differences between JFET and MOSFET
- Biasing MOSFET
- FET applications
- CMOS
Module 5 (2nd half notes) imp Question and Answers
D/A conversion and A/D conversion
important Question and Answers
important Question and Answers
Wednesday, November 8, 2017
Wednesday, November 1, 2017
Logic Design Jan 2014 solved Question Paper as per ADE syllabus
Logic Design Jan 2014 solved Question Paper as per ADE syllabus
Logic Design July 2013 solved Question Paper as per ADE syllabus
Logic Design July 2013 solved Question Paper as per ADE syllabus
Module 4 (2nd half) Registers notes
Module 4 (2nd half) Registers notes
1. SISO
2. SIPO
3. PISO
4. PIPO
5. USR
6. Apllications of Registers
1. SISO
2. SIPO
3. PISO
4. PIPO
5. USR
6. Apllications of Registers
Module 3 (2nd half) and Module 4 (1st half) Flipflop notes
Module 3 (2nd half) and Module 4 (1st half) Flipflop notes
1. RS flipflop
2. Gated flipflops
3. Edge triggered flipflops
4. Master Slave flipflops
5. Switch contact bounce circuits.
6. Flipflop timing
7. Various representation of flipflops
1. RS flipflop
2. Gated flipflops
3. Edge triggered flipflops
4. Master Slave flipflops
5. Switch contact bounce circuits.
6. Flipflop timing
7. Various representation of flipflops
Module 2 Notes
Module 2 Handouts for your reference
- Prerequisites
- Basic Gates
- K-Map
- SOP
- POS
- Dont Care
- QM
MODULE 3 (first half) NOTES
MODULE 3 (first half) NOTES
SYLLABUS:
SYLLABUS:
- Multiplexers
- De-multiplexers
- 1 of 16 Decoders
- BCD to Decimal Decoders
- Seven Segment Decoders
- Encoders
- Exclusive-OR gates
- Parity Generator and Checkers
- Magnitude Comparator
- PAL and PLA
- HDL implementation of Data Processing Circuits
- Arithmetic Logic Circuits and ALU
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